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M95512-W M95512-R
512 Kbit Serial SPI bus EEPROM with high speed clock
Features

Compatible with SPI bus serial interface (Positive clock SPI modes) Single supply voltage: - 2.5 V to 5.5 V for M95512-W - 1.8 V to 5.5 V for M95512-R High speed - 5 MHz clock rate - 5 ms Write time Status Register Hardware Protection of the Status Register Byte and Page Write (up to 128 bytes) Self-timed programming cycle Adjustable size read-only EEPROM area Enhanced ESD Protection More than 1 000 000 Write cycles More than 40-year data retention Packages - ECOPACK(R) (RoHS compliant)
TSSOP8 (DW) 169 mils width SO8 (MN) 150 mils width

July 2008
Rev 9
1/39
www.st.com 1
Contents
M95512-W, M95512-R
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1 4.1.2 4.1.3 4.1.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 4.3 4.4 4.5
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Protection and Protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 6.2 6.3 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M95512-W, M95512-R 6.3.2 6.3.3 6.3.4
Contents WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 6.5 6.6
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 8
ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 25 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.1 8.2 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 10 11 12 13
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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List of tables
M95512-W, M95512-R
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write-Protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M95512-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating conditions (M95512-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M95512-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M95128-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC characteristics (M95512-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AC characteristics (M95512-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SO8N - 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TSSOP8 - 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 34 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Available M95512x products (package, voltage range, temperature grade) . . . . . . . . . . . 36 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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M95512-W, M95512-R
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SO8N - 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 33 TSSOP8 - 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 34
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Description
M95512-W, M95512-R
1
Description
These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized as 65536 x 8 bit. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD). Figure 1. Logic diagram
VCC
D C S W HOLD M95xxx
Q
VSS
AI01789C
Table 1.
Signal names
Signal name Function Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply voltage Ground Input Input Output Input Input Input Direction
C D Q S W HOLD VCC VSS
6/39
M95512-W, M95512-R Figure 2. SO and TSSOP connections
M95xxx S Q W VSS 1 2 3 4 8 7 6 5
AI01790D
Description
VCC HOLD C D
1. See Section 11: Package mechanical data for package dimensions, and how to identify pin-1.
7/39
Signal description
M95512-W, M95512-R
2
Signal description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 11 and Table 12). These signals are described next.
2.1
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
8/39
M95512-W, M95512-R
Signal description
2.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
9/39
Connecting to the SPI bus
M95512-W, M95512-R
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 3. Bus master and memory devices on the SPI bus
VSS VCC R SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD SPI Bus Master R CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD SPI Memory Device VCC VSS R SPI Memory Device CQD VCC VSS R SPI Memory Device CQD VCC VSS
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 3 shows an example of three memory devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, the other devices are high impedance. The pull-up resistor R (represented in Figure 3) ensures that no device is selected if the Bus Master leaves the S line in the high impedance state. In applications where the Bus Master might enter a state where all inputs/outputs SPI lines are in high impedance at the same time (for example, if the Bus Master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high). This ensures that S and C do not become high at the same time, and so, that the tSHCH requirement is met.
10/39
M95512-W, M95512-R
Connecting to the SPI bus
The typical value of R is 100 k assuming that the time constant R*Cp (Cp = parasitic , capacitance of the bus line) is short enough, as the S and C lines must reach the correct state (S = high and C = low) while the SPI bus is in high impedance. Example: Cp = 50 pF, that is R*Cp = 5 s <=> the application must ensure that the Bus Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 s.
3.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) SPI modes supported
Figure 4.
CPOL CPHA C
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
11/39
Operating features
M95512-W, M95512-R
4
4.1
4.1.1
Operating features
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 7 and Table 8.). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
4.1.2
Device reset
In order to prevent inadvertent Write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the POR threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 7 and Table 8). When VCC passes over the POR threshold, the device is reset and in the following state:

in the Standby Power mode deselected (note that when the device is deselected it is necessary to apply a falling edge on Chip Select (S) prior to issuing any new instruction, otherwise the instruction is not executed) Status register values: - - - the Write Enable Latch (WEL) bit is reset to 0 the Write In Progress (WIP) bit is reset to 0 the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
4.1.3
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 3). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been high, prior to going low to start the first operation. The VCC rise time must not vary faster than 1 V/s. Important note: When VCC passes over the POR threshold (see Section 4.1.2: Device reset), the device is reset and enters the Standby Power mode. However, the device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] ranges defined in Table 7 and Table 8.
12/39
M95512-W, M95512-R
Operating features
4.1.4
Power-down
During power-down (continuous decrease in VCC below the minimum VCC operating voltage defined in Table 7 and Table 8), the device must be:

deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC) in Standby Power mode (that is there should not be any internal write cycle in progress).
4.2
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The device consumes ICC, as specified in Table 12. When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to ICC1.
4.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as Serial Clock (C) already being low (as shown in Figure 5). The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as Serial Clock (C) already being low. Figure 5 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. Figure 5. Hold condition activation
C
HOLD
Hold Condition
Hold Condition
AI02029D
13/39
Operating features
M95512-W, M95512-R
4.4
Status Register
Figure 6 shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a detailed description of the Status Register bits
4.5
Data Protection and Protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms:

Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write (WRITE) instruction completion

The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only. The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits in the Status Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:
The `last bit of the instruction' can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). The `next rising edge of Serial Clock (C)' might (or might not) be the next bus transaction for some other device on the SPI bus. Write-Protected block size
Status Register Bits Protected Block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory Array Addresses Protected none C000h - FFFFh 8000h - FFFFh 0000h - FFFFh
Table 2.
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M95512-W, M95512-R
Memory organization
5
Memory organization
The memory is organized as shown in Figure 6. Figure 6.
HOLD W S C D Q Control Logic
Block diagram
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Register
Size of the Read only EEPROM area
Y Decoder
1 Page
X Decoder
AI01272C
15/39
Instructions
M95512-W, M95512-R
6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3. Instruction set
Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction Format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Instruction WREN WRDI RDSR WRSR READ WRITE
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. Figure 7. Write Enable (WREN) sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
16/39
M95512-W, M95512-R
Instructions
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Write Disable (WRDI) sequence
Figure 8.
S 0 C Instruction D High Impedance Q
AI03750D
1
2
3
4
5
6
7
17/39
Instructions
M95512-W, M95512-R
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 9. The status and control bits of the Status Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 4) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4.
b7 SRWD 0 0 0 BP1 BP0 WEL
Status Register format
b0 WIP
Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit
18/39
M95512-W, M95512-R Figure 9.
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 Status Register Out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instructions Read Status Register (RDSR) sequence
0
7
AI02031E
19/39
Instructions
M95512-W, M95512-R
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before a WRSR instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Write Status Register (WRSR) instruction is issued by driving Chip Select (S) low, sending the instruction code and the data byte on Serial Data input (D) and driving Chip Select (S) high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write cycle whose duration is tW (specified in Table 13 and Table 14). The instruction sequence is shown in Figure 10. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is also reset when the Write cycle tW is complete. The Write Status Register (WRSR) instruction allows the user to change the values of the BP1, BP0 and SRWD bits:

The Block Protect (BP1, BP0) bits define the size of the area to be treated as read-only, as defined in Table 5. The SRWD bit (Status Register Write Disable bit), depending on the signal applied on the Write Protect pin (W), allows the user to set or reset the write protection mode of the Status Register. When the Status Register is in the Write-protected mode, the Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated upon completion of the WRSR instruction (after tW). The Write Status Register (WRSR) instruction has no effect on Status Register bits b6, b5, b4, b1, b0. They are always read as 0. Figure 10. Write Status Register (WRSR) sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
20/39
M95512-W, M95512-R Table 5. Protection modes
Mode Write Protection of the Status Register
Instructions
W SRWD Signal Bit 1 0 1 0 0 1
Memory content Protected area(1) Unprotected area(1)
Status Register is Writable Software (if the WREN instruction Protected has set the WEL bit) Write Protected (SPM) The values in the BP1 and BP0 bits can be changed Status Register is Hardware Hardware write protected Protected The values in the BP1 and Write Protected (HPM) BP0 bits cannot be changed
Ready to accept Write instructions
0
1
Ready to accept Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
The protection features of the device are summarized in Table 5. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven high or low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W):
If Write Protect (W) is driven high, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) low or by driving Write Protect (W) low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) high. If Write Protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
21/39
Instructions
M95512-W, M95512-R
6.5
Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
S 0 C Instruction 16-Bit Address 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI01793D
22/39
M95512-W, M95512-R
Instructions
6.6
Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle triggered by the rising edge of Chip Select (S) continues for a period tW (as specified in Table 13 and Table 14), at the end of which the Write in Progress (WIP) bit is reset to 0. In the case of Figure 12, Chip Select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. If, though, Chip Select (S) continues to be driven low, as shown in Figure 13., the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 128 bytes). The instruction is not accepted, and is not executed, under the following conditions:

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) if a Write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Figure 12. Byte Write (WRITE) sequence
S 0 C Instruction 16-Bit Address Data Byte 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
AI01795D
23/39
Instructions Figure 13. Page Write (WRITE) sequence
S 0 C Instruction 16-Bit Address 1 2 3 4 5 6 7 8 9 10
M95512-W, M95512-R
20 21 22 23 24 25 26 27 28 29 30 31
Data Byte 1
D
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 Data Byte 3 Data Byte N
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
AI01796D
24/39
M95512-W, M95512-R
ECC (Error Correction Code) and Write cycling
7
ECC (Error Correction Code) and Write cycling
The M95512-W and M95512-R devices offer an ECC (Error Correction Code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes making up the word. It is therefore recommended to write by words of 4 bytes in order to benefit from the larger amount of Write cycles. The M95512-W and M95512-R devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets.
8
8.1
Power-up and delivery state
Power-up state
After Power-up, the device is in the following state:

Standby Power mode Deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started). Not in the Hold Condition Write Enable Latch (WEL) is reset to 0 Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits).
8.2
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
25/39
Maximum rating
M95512-W, M95512-R
9
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Symbol TA TSTG TLEAD VO VI VCC VESD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature Lead temperature during soldering Output voltage Input voltage Supply voltage Electrostatic discharge voltage (Human Body Model)(2) Min. -40 -65 See -0.50 -0.50 -0.50 -4000 Max. 130 150 note (1) VCC+0.6 6.5 6.5 4000 Unit C C C V V V V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500, R2=500)
26/39
M95512-W, M95512-R
DC and AC parameters
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7.
Symbol VCC TA Supply voltage Ambient operating temperature (device grade 6) Ambient operating temperature (device grade 3)
Operating conditions (M95512-W)
Parameter Min. 2.5 -40 -40 Max. 5.5 85 125 Unit V C C
Table 8.
Symbol VCC TA
Operating conditions (M95512-R)
Parameter Supply voltage Ambient operating temperature Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 9.
Symbol CL
AC measurement conditions
Parameter Load capacitance Input Rise and Fall times Input Pulse voltages Input and output timing reference voltages Min. 30 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
Figure 14. AC measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 10.
Symbol COUT CIN
Capacitance(1)
Parameter Output capacitance (Q) Input capacitance (D) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V VIN = 0 V Min. Max. 8 8 6 Unit pF pF pF
1. Not 100% tested.
27/39
DC and AC parameters Table 11.
Symbol ILI ILO
M95512-W, M95512-R DC characteristics (M95512-W)
Parameter Test condition specified in Table 7 VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5 V, Q = open Min. Max. 2 2 3 5 6 5 -0.45 0.7 VCC VCC = 2.5 V and IOL = 1.5 mA or VCC = 5 V and IOL = 2 mA VCC = 2.5 V and IOH = -0.4 mA or 0.8 VCC VCC = 5 V and IOH = -2 mA 0.3 VCC VCC+1 0.4 Unit A A mA mA mA A V V V V
Input leakage current Output leakage current
ICC
Supply current (Read)
ICC0(1) ICC1 VIL VIH VOL VOH
Supply current (Write) Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage Output high voltage
During tW, S = VCC, 2.5 V < VCC < 5.5 V S = VCC, VIN = VSS or VCC, 2.5 V < VCC < 5.5 V
1. Characterized value, not tested in production.
Table 12.
Symbol ILI ILO ICC ICC0(1) ICC1 VIL VIH VOL VOH
DC characteristics (M95128-R)
Parameter Input leakage current Output leakage current Supply current (Read) Supply current (Write) Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage Output high voltage IOL = 0.15 mA, VCC = 1.8 V IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC Test condition specified in Table 8 VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 2 MHz, VCC = 1.8 V, Q = open During tW, S = VCC, 1.8 V < VCC < 2.5 V S = VCC, VIN = VSS or VCC, 1.8 V < VCC < 2.5 V -0.45 0.7 VCC Min Max 2 2 1 3 3 0.3 VCC VCC+1 0.3 Unit A A mA mA A V V V V
1. Characterized value, not tested in production.
28/39
M95512-W, M95512-R Table 13. AC characteristics (M95512-W)
DC and AC parameters
Test conditions specified in Table 9 and Table 7 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH (1) tCL
(1) (2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency S active setup time
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH tCHCL
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time
tCLQV tCLQX tQLQH tQHQL
(2) (2)
tHHQV tHLQZ (2) tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
29/39
DC and AC parameters Table 14. AC characteristics (M95512-R)
Test conditions specified in Table 9 and Table 8 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH (1) tCL
(1) (2) (2)
M95512-W, M95512-R
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency
Parameter
Min. D.C. 200 200 200 200 200 200 200
Max. 2
Unit MHz ns ns ns ns ns ns ns
S active setup time S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH tCHCL
1 1 40 50 140 90 0 0 250 150 0 100 100 100 250 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time
tCLQV tCLQX tQLQH tQHQL
(2) (2)
tHHQV tHLQZ (2) tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
30/39
M95512-W, M95512-R Figure 15. Serial input timing
DC and AC parameters
tSHSL S tCHSL C tDVCH tCHCL tCHDX D MSB IN LSB IN tCL tCLCH tSLCH tCH tCHSH tSHCH
Q
High impedance
AI01447d
Figure 16. Hold timing
S tHLCH tCLHL C tCLHH tHLQZ Q tHHQV tHHCH
HOLD
AI01448c
31/39
DC and AC parameters Figure 17. Serial output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D LSB IN
ADDR
M95512-W, M95512-R
tSHSL
tCLCH
tCHCL
tCL
tSHQZ
AI01449f
32/39
M95512-W, M95512-R
Package mechanical data
11
Package mechanical data
In order to meet environmental requirements, ST offers the M95512-W in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 18. SO8N - 8 lead plastic small outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 15.
SO8N - 8 lead plastic small outline, 150 mils body width, package mechanical data
millimeters inches(1) Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 1.04 5.00 6.20 4.00 - 0.50 8 1.27 0.0409 0.1929 0.2362 0.1535 0.05 0.189 0.2283 0.1496 0.0098 0 0.0157 0.25 0.0039 0.0492 0.011 0.0067 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 0.0197 8 0.05 Typ Min Max 0.0689 0.0098
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
1. Values in inches are converted from mm and rounded to 4 decimal digits.
33/39
Package mechanical data
M95512-W, M95512-R
Figure 19. TSSOP8 - 8 lead thin shrink small outline, package outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
1. Drawing is not to scale.
Table 16.
Symbol
TSSOP8 - 8 lead thin shrink small outline, package mechanical data
millimeters Typ Min Max 1.200 0.050 1.000 0.800 0.190 0.090 0.150 1.050 0.300 0.200 0.100 3.000 0.650 6.400 4.400 0.600 1.000 0 8 8 2.900 - 6.200 4.300 0.450 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ inches(1) Min Max 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295
A A1 A2 b c CP D e E E1 L L1 N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
34/39
M95512-W, M95512-R
Part numbering
12
Part numbering
Table 17.
Example:
Ordering information scheme
M95512 - W MN 6 T P /AB
Device type M95 = SPI serial access EEPROM
Device function 512 = 512 Kbit (65536 x 8)
Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V
Package MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width)
Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Device tested with high reliability certified flow(1). Automotive temperature range (-40 to 125 C)
Option blank = Standard packing T = Tape and reel packing
Plating technology P or G = ECOPACK(R) (RoHS compliant)
Process /AB = F8L(2)
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. The process letter only concerns device grade 3 devices.
35/39
Part numbering
M95512-W, M95512-R
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 18. Available M95512x products (package, voltage range, temperature grade)
Package
M95512-W
2.5 V to 5.5 V Range 6 Range 3 Range 6
M95512-R 1.8 V to 5.5 V Range 6 Range 6
SO8 (MN) TSSOP (DW)
36/39
M95512-W, M95512-R
Revision history
13
Revision history
Table 19.
Date Jan-1999
Document revision history
Revision 1.0 Document written Document reformatted using the new template Voltage range -S added, and -R removed Instruction Sequence illustrations updated Announcement made of planned upgrade to 10 MHz clock for the 5V, -40 to 85C, range Table of contents, and Pb-free options added. VIL(min) improved to -0.45V. Voltage range -R added, and -S removed Old versions of document completely replaced by one rewritten from M95256 AC and DC characteristics tables updated with the performance data of the new device identified with the process letter "A". Table 1., Product List added. AEC-Q100-002 compliance. Device Grade information clarified. tHHQX, tCHHL and tCHHH corrected to tHHQV, tCLHL and tCLHH, respectively. M95512 part number with 4.5V to 5.5V operating voltage range removed (related tables removed). Document status changed to Preliminary Data. Updated Figure 3: Bus master and memory devices on the SPI bus and Figure 16: Hold timing. Power On Reset information clarified. Protected Array Addresses modified in Table 2: Write-Protected block size. Ambient Operating Temperature value added in Table 6: Absolute maximum ratings. Supply Current (ICC) value modified for 10 MHz in Table 11: DC characteristics (M95512-W). All values modified in Table 14: AC characteristics (M95512-R). Document status changed to Datasheet. Document reformatted. Packages are ECOPACK(R) compliant. 10 MHz frequency removed. VCC supply voltage and VSS ground descriptions added. Figure 3: Bus master and memory devices on the SPI bus modified and explanatory paragraph added. Power-up and Power On Reset paragraphs replaced by Section 4.1: Supply voltage (VCC). Section 7: ECC (Error Correction Code) and Write cycling added. TA max modified in Table 7: Operating conditions (M95512-W). Note modified below Table 10: Capacitance. CL modified in and Table 9: AC measurement conditions. VIL max and ICC0 test conditions modified in Table 12: DC characteristics (M95128-R). ICC modified in Table 11: DC characteristics (M95512-W), ICC0 added to Table 11 and Table 12: DC characteristics (M95128-R) modified. Table 14: AC characteristics (M95512-R) modified. tSHQZ end timing line moved back in Figure 17: Serial output timing. SO8N package specifications updated (see Figure 18 and Table 15). Blank removed below Plating technology in Table 17: Ordering information scheme. The device endurance is specified at more than 1 000 000 (1 million) cycles (corrected on page 1). Changes
13-Feb-2002
2.0
05-Dec2003 02-Apr-2004
3.0 4.0
03-Jan-2005
5.0
30-Jun-2005
6.0
06-Feb-2007
7
05-Jun-2007
8
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Revision history Table 19.
Date
M95512-W, M95512-R Document revision history
Revision Changes M95512-W is now available in the device grade 3 (automotive temperature range), see Table 7 on page 27). Section 4.1: Supply voltage (VCC) on page 12 updated. Section 6.4: Write Status Register (WRSR) on page 20 and Section 6.6: Write to Memory Array (WRITE) on page 23 clarified. ICC0 modified in Table 11: DC characteristics (M95512-W). Figure 15: Serial input timing, Figure 16: Hold timing and Figure 17: Serial output timing updated. Package mechanical data values in inches are calculated from the millimeter values and rounded to four decimal digits (see Section 11: Package mechanical data). Table 18: Available M95512x products (package, voltage range, temperature grade) added.. Small text changes.
03-Jul-2008
9
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M95512-W, M95512-R
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